The described embodiments lie generally in the field of digital audio coding and decoding and in particular to data conversion circuits and methods with automatic input signal detection and master mode output clock generation.
Audio support is provided for many modern computer, telephony, and other electronics applications. An important component in many digital audio information processing systems is the Pulse-Code Modulated (xe2x80x9cPCMxe2x80x9d) decoder. Generally, the decoder receives data in a compressed form and converts that data into PCM data. The decompressed digital PCM data is then passed on for further processing, such as filtering, expansion or mixing, conversion into analog form, and eventually into audible tones.
One form of compressed audio data is the S/PDIF format, which can be converted to PCM data with a digital audio receiver chip. The standard PCM data formats contain a high rate clock (xe2x80x9cMCLKxe2x80x9d), a sample rate clock (xe2x80x9cLRCKxe2x80x9d), which is used to select between the left and right channel data, a data signal (xe2x80x9cSDATAxe2x80x9d) that contains signal information at the MCLK rate, and a sample signal (xe2x80x9cSCLKxe2x80x9d), which latches in the data signal. This method allows audio samples with various sample rates and bits per sample to be input to Digital-to-Analog Converters (xe2x80x9cDACsxe2x80x9d) in a serial fashion.
Sampling rates of 48 kHz, 96 khz, and 192 khz are common and will be referred to in this specification as single-speed, double-speed, and quad-speed sampling modes, respectively. To convert the PCM data properly, DACs must be set to sample the incoming data at the proper rate. In the prior art, DACs have used programmed bits in a register or have used external pin settings to set their properties according to the speed sampling mode of the incoming PCM or other input format data stream.
The principles of the present invention are embodied in circuits, methods and systems, which utilize automatic frequency detection to selectively generate clock signals of selected frequencies from a single input signal. According to one particular embodiment, a data converter is disclosed which includes first and second signal paths receiving an input signal having an input frequency, the first signal path dividing the input frequency by a first divisor and the second signal path dividing the input frequency by a second divisor, the second divisor being greater than the first divisor. A selector selects between an output of the first signal path and an output from the second signal path in response to a state of a control signal. Control circuitry monitors a selector output signal frequency and selectively resets the state of the control signal to set the selector output frequency to a desired frequency. Additional embodiments of the inventive principles support the generation of one or more output signals of selected frequencies during master mode operations from the signal output from the selector.
Circuits, methods, and systems embodying the principles of the present invention advantageously allow for the detection of the frequency of a received signal and the automatic generation of internal clock signal having a frequency corresponding to an associated speed mode. During master mode operations, the internal clock signal is further divided in response to a minimal number of mode control signals to generate one or more output clock signals of frequencies corresponding to the speed mode. Hence, a single received clock of a given frequency is provided and at least one output clock corresponding to the appropriate speed mode is output with minimal external control intervention.